In the existing television system, a so-called interlaced scanning system is carried out. That is, one picture (frame) is transmitted by two vertical scannings (fields). This interlaced scanning system is considered in order to increase the number of scanning lines as much as possible in a limited frequency band without a flicker being perceived by a viewer.
However, in the CCIR system employed mainly in European countries, the field frequency is 50 Hz. By this frequency, the flicker can not be removed completely and the flicker becomes conspicuous particularly when the brightness of the television picture is high.
Therefore, in the prior art, such a television receiver is proposed that a television picture is displayed at a field frequency twice the normal field frequency. FIG. 1 shows an example thereof.
In the figure, reference numeral 1 designates an antenna, 2 a tuner, 3 a video intermediate frequency amplifier, and 4 a video detecting circuit. The video detecting circuit 4 produces a video signal Sv of interlaced system of 625 lines/50 fields and 2:1.
This video signal Sv is converted to a digital signal by an A/D converter 5 and then fed to a converting circuit 6 so as to be converted to a field twice normal speed video signal with field frequency twice the normal field frequency.
The converting circuit 6 is formed of field memories (random access memories having a storage capacity of picture elements of one field period (1V)) 6a and 6b and switching circuits 6c and 6d. The switching circuit 6c is changed in position to the sides of the memories 6a and 6b at every field period 1V, while the switching circuit 6d is changed in position reversely. The memory selected by the switching circuit 6c is supplied with a write clock pulse having a timing corresponding to the aboye-described picture elements, while the memory selected by the switching circuit 6d is supplied with a read clock pulse with frequency twice the frequency of the write clock pulse.
The video signal Sv converted to the digital signal by the A/D converter 5 is supplied through the switching circuit 6c to the memories 6a and 6b by one field each at every field period 1V in which it is written. The video signal of one field amount, which is written in the memories 6b and 6a during a field period 1V just before the above-mentioned field period, is read out therefrom continuously twice with a cycle of 1/2 V. This video signal is derived through the switching circuit 6d. In other words, the switching circuit 6d delivers a field twice normal speed video signal Sv, that is, at a double field frequency.
This video signal Sv' is converted to an analog signal by a D/A converter 7 and then fed to a signal processing circuit 8. Then, from the signal processing circuit 8, red, green and blue primary color signals R, G and B are produced and then supplied to an image receiving tube 9, respectively.
The video signal Sv derived from the video detecting circuit 4 is supplied to a vertical synchronizing separating circuit 10. A vertical synchronizing signal Pv derived from the separating circuit 10 is multiplied twice by a frequency multiplier 11 to be a signal with frequency twice the ordinary frequency. This signal is supplied through a vertical deflecting circuit 12 to a deflecting coil 13.
The video signal Sv' derived from the D/A converter 7 is supplied to a horizontal synchronizing separating circuit 14. A horizontal synchronizing signal P.sub.H ' (having the frequency twice the normal frequency) derived from the separating circuit 14 is supplied through a horizontal deflecting circuit 15 to the deflecting coil 13.
Since the example of the television receiver shown in FIG. 1 is constructed as described above, the primary color signals R, G and B each of which has the field frequency twice the normal field frequency are supplied to the picture receiving tube 9 and the horizontal and vertical deflection scannings are carried out at scanning speed twice the normal scanning speed, and hence a color picture with the field frequency twice the normal field frequency is displayed on the picture receiving tube 9. Accordingly, also in the above CCIR system, the field frequency becomes 100 Hz which is twice the normal field frequency so that the viewer feels no flicker.
In the case of the example shown in FIG. 1, however, the horizontal synchronization of the video signal Sv' derived from the converting circuit 6 is disturbed cyclically so that a distortion occurs in the upper portion of the picture screen.
That is, the write-in state of the video signal Sv derived from the video detecting circuit 4 in the memories 6a and 6b is expressed as shown in FIG. 2A, in which references F.sub.1 and F.sub.2 designate first and second fields, respectively. The video signal Sv' from the converting circuit 6 is expressed as shown in FIG. 2B. In the figure, arrows represent the positions of the vertical synchronizing signals. As will be clear from FIG. 2B, in the video signal Sv', the phase of the horizontal synchronization is displaced by 180.degree. at every two fields, or at every 1/50 seconds (shown by broken line arrows), whereby the synchronization on the upper portion of the picture screen is disturbed, resulting in a picture distorion.
Therefore, the present applicant has proposed a television receiver which is free of such picture distortion and FIG. 3 shows an example thereof. In FIG. 3, like parts corresponding to those of FIG. 1 are marked with the same references.
In the figure, the video signal Sv derived from the video detecting circuit 4 is converted to the digital signal by the A/D converter 5 and then fed to a converting circuit 16 so as to be converted to the field twice normal speed video signal with the frequency twice the normal field frequency.
The converting circuit 16 is formed of field memories (random access memories) 16a and 16b having storage capacities of picture elements of 313 horizontal periods (313H) and 312 horizontal periods (312H) and switching circuits 16c and 16d. The switching circuit 16 is changed in position alternately to the side of the memory 16a during each period of 313H and to the side of the memory 16b during each period of 312H, while the switching circuit 16d is changed in position in the reverse manner. These change-overs of the change-over switches 16c and 16d are controlled by a control circuit 17. This control circuit 17 is supplied with horizontal and vertical synchronizing signals P.sub.H and P.sub.V which are separated from the video signal Sv by a synchronizing separating circuit 18.
The memory selected by the switching circuit 16c is supplied with the write clock pulse having the timing corresponding to the above picture elements, while the memory selected by the switching circuit 16d is supplied with a read clock pulse with the frequency twice the frequency of the write clock pulse.
The video signal Sv converted to the digital signal by the A/D converter 5 is supplied through the switching circuit 16c to the memories 16a and 16b in which it is alternately written during each period of 313H and 312H. FIG. 4A shows the write-in state of the memories 16a and 16b, in which references F.sub.1 and F.sub.2 represent the first and second fields, respectively. During the periods of 313H and 312H in which the video signal is being written in one of the memories, the video signal written in the other of the memories 16b and 16a during the periods just before the above 312H and 313H are read out therefrom twice continuously. This signal is derived through the switching circuit 16d as a field twice normal speed video signal Sv*. FIG. 4B shows the video signal Sv* which is derived through the switching circuit 16d, in which the field portions corresponding to those of FIG. 4A are marked with the same references. By the way, due to the difference between the write time and the read time, extra or lack of one line amount per field is produced in the video signal Sv*.
In FIG. 4B, at the portions of, for example, the F.sub.1 and F.sub.1 fields (the portions read out from the memory 16a), 313 lines are not read out because of a time relation. Further, at, for example, the F.sub.2 and F.sub.2 field portions (the portions read out from the memory 16b), the video signal of one line amount is lacked and during that period, the reading operation is stopped and the video signal of one line amount is lacked (shown by one-dot chain lines). The extra and lack of the video signal of one line amount as mentioned above occur in the vertical blanking period so that in practice, this does not disturb the television picture.
The writing in and reading out from the memories 16a and 16b are controlled by the control circuit 17.
The video signal Sv* derived from the switching circuit 16d is converted to the analog signal by the D/A converter 7 and then fed to the signal processing circuit 8. Then, the red, green and blue primary color signals R, G and B are produced from the signal processing circuit 8 and then fed to the picture receiving tube 9, respectively.
The control circuit 17 produces a vertical synchronizing signal Pv* at the timing shown by arrows in FIG. 4B. More particularly, the vertical synchronizing signal Pv* is produced at the beginning of the first F.sub.1 field, at the timing after 312 lines from the preceding line, namely, at the beginning of the second F.sub.1 field, at the timing after 311.5 lines from the preceding line, at the timing after 313 lines from the preceding line and at the timing after 313.5 lines from the preceding line, or the beginning of the first F.sub.1 field, hereinafter similarly. This synchronizing signal Pv* is supplied through the vertical deflecting circuit 12 to the deflecting coil 13 which then carries out the vertical deflection scanning. When the synchronizing signal Pv* is produced at the above-mentioned timing, in the same F.sub.1 field and F.sub.2 fields, the scanning lines are formed at the same positions and the scanning lines respectively formed at the F.sub.1 field and F.sub.2 field are displaced by 1/2 scanning line spacing each. In other words, the interlaced relation of the video signal Sv is kept as it is.
The video signal Sv* from the D/A converter 7 is supplied to the horizontal synchronizing separating circuit 14. A horizontal synchronizing signal P.sub.H * (having the frequency twice the normal frequency) derived from the separating circuit 14 is supplied through the horizontal deflecting circuit 15 to the deflecting coil 13 by which the horizontal deflection scanning is carried out.
According to the example of the television receiver shown in FIG. 3, the horizontal synchronization of the video signal Sv* becomes continuous as shown in FIG. 4B so that the synchronization can be prevented from being disturbed by the insuccessive horizontal synchronization unlike the example of FIG. 1 and thus no picture distortion is produced.
However, in the example of FIG. 3, since the generation timing of the vertical synchronizing signal Pv* is determined such that the scanning lines of the same F.sub.1 fields and F.sub.2 fields are formed at the same positions (see the arrows in FIG. 4B), the vertical cycle is made different very slightly and not becomes exactly 1/100 second=10 m sec.
By the way, in the television receiver, in order to correct left and right pincushion distortions, a parabolic wave current with the vertical synchronizing frequency is superposed on the horizontal deflection current. In this case, since the cycle of the vertical synchronizing signal Pv* is different (see FIG. 5A) as mentioned above, also the vertical deflection current becomes correspondingly different (see FIG. 5B). Further, the horizontal deflection current waveform is changed at every vertical cycle (see FIG. 5C). As described above, since the horizontal deflection current waveform is different, a jitter appears in the right and left ends of the picture screen at a fundamental frequency of 25 Hz (four field cycles of F.sub.1, F.sub.1, F.sub.2, and F.sub.2). This jitter becomes conspicuous much if the deflection angle becomes larger.
To remove this jitter, it may be considered to correct the horizontal deflection current waveform by the deflecting system. However, the correction thereof is very difficult and requires a special deflection correcting circuit.
In this case, since the cycle of the vertical synchronizing signal Pv* becomes different (see FIG. 5A), also the vertical deflecting current becomes different at every vertical cycle (see FIG. 5B) but this does not exert so serious bad influence on the picture screen.